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1 isl7457srh caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2009, 2011. all rights reserved intersil (and design) is a trademark owned by in tersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. radiation hardened, see hardened, non-inverting, quad cmos driver isl7457srh the isl7457srh is a radiation hardened, see hardened, high speed, non-inverting, quad cmos driver. it is capable of running at clock rates up to 40mhz and features 2a typical peak drive capability and a nominal on-resistance of just 3.5 . the isl7457srh is ideal for driving highly capacitive loads, such as storage and vertical clocks in ccd applications. it is also well suited to level-shifting and clock-driving applications. each output of the isl7457srh can be switched to either the high (v h ) or low (v l ) supply pins, depending on the related input pin. the inputs are compatible with both 3.3v and 5v cmos logic. the output enable (oe) pin can be used to put the outputs in to a high-impedance state. this is especially useful in ccd applications, where the driver should be disabled during power down. the isl7457srh also features very fast rise and fall times which are typically matched to within 1ns. the propagation delay is also matched between rising and falling edges to typically within 1.5ns. the isl7457srh is available in a 16 lead ceramic flatpack package and specified for operation over the full -55c to +125c ambient temperature range. specifications for rad hard qml devices are controlled by the defe nse supply center in columbus (dscc). the smd numbers listed here must be used when ordering. detailed electrical specifications for these devices are contained in smd 5962-08230. a ?hot-link? is provided on our website for downloading. pin configuration isl7457srh (16 ld flatpack) top view features ? electrically screened to smd 5962-08230 ? qml qualified per mil-prf-38535 requirements ? full mil-temp range operation . t a = -55 c to +125 c ?radiation hardness - tid [50-300 rad(si)/s] . . . . . . . .10krad(si) min ? see hardness - let (sel and seb immunity)40mev/mg/cm 2 min -let [set = v out < 15v, t < 500ns] . . . . . . . 40mev/mg/cm 2 ? 4 channels ? clocking speeds up to 40mhz ? 11ns/12ns typical t r /t f with 1nf load (15v bias) ? 1ns typical rise and fall time match (15v bias) ? 1.5ns typical prop delay match (15v bias) ? low quiescent current - < 1ma typical ? fast output enable function - 12ns typical (15v bias) ? wide output voltage range -0v v l 8v -2.5v v h 16.5v ? 2a typical peak drive current (15v bias) ?3.5 typical on-resistance (15v bias) ? input level shifters ? 3.3v/5v cmos compatible inputs applications ? ccd drivers, clock/line drivers, level-shifters ina oe inb v l gnd nc inc ind 2 3 4 5 6 7 8 116 15 14 13 12 11 10 9 v s + outa outb nc v h outc outd v s - may 16, 2011 fn6874.1
2 fn6874.1 may 16, 2011 ordering information ordering number part number temp. range (c) package pkg. dwg. # 5962d0823001qxc isl7457srhqf -55 to +125 16 ld flatpack k16.a 5962d0823001vxc isl7457srhvf -55 to +125 16 ld flatpack k16.a 5962d0823001v9a isl7457srhvx -55 to +125 die isl7457srhf/proto isl7457srhf/proto -55 to +125 16 ld flatpack k16.a isl7457srhx/sample isl7457srhx/sample -55 to +125 die isl7457srh
3 fn6874.1 may 16, 2011 electrical specifications typical values reflect v s + = v h = 5v, v s - = v l = 0v, oe = v s +, t a = +25c unless otherwise specified. parameter description co ndition min typ max unit input v ih logic ?1? input voltage 1.3 v i ih logic ?1? input current inx = v s +10na v il logic ?0? input voltage 1.23 v i il logic ?0? input current inx = 0v -5 na c in input capacitance 5.7 pf r in input resistance 500 m output r oh on resistance v h to outx inx = v s +, i outx = -100ma 8 r ol on resistance v l to outx inx = 0v, i outx = +100ma 6 i leak+ positive output leakage current inx = v s +, oe = 0v, outx = v s +5na i leak- negative output leakage current inx = v s +, oe = 0v, outx = v s --5na power supply i s+ v s + supply current inx = 0v and v s +0.2ma i s- v s - supply current inx = 0v and v s +-0.2ma i h v h supply current inx = 0v and v s +0.1a i l v l supply current inx = 0v and v s +0.1a switching characteristics t r rise time inx = 0v to 4.5v step, c l = 1nf 23 ns t f fall time inx = 4.5v to 0v step, c l = 1nf 20 ns t rf t r , t f mismatch c l = 1nf 3 ns t d + turn-on delay time inx = 0v to 4.5v step, c l = 1nf 20 ns t d - turn-off delay time inx = 4.5v to 0v step, c l = 1nf 22 ns t dd t d +, t d - mismatch c l = 1nf 2 ns t enable enable delay time inx = v s +, oe = 0v to 4.5v step, r l = 1k 21 ns t disable disable delay time inx = v s +, oe = 4.5v to 0v step, r l = 1k 46 ns isl7457srh
4 fn6874.1 may 16, 2011 electrical specifications typical values reflect v s + = v h = 15v, v s - = v l = 0v, oe = v s +, t a = +25c unless otherwise specified. parameter description condition min typ max unit input v ih logic ?1? input voltage 1.63 v i ih logic ?1? input current inx = v s +10na v il logic ?0? input voltage 1.4 v i il logic ?0? input current inx = 0v -5 na c in input capacitance 5.7 pf r in input resistance 1.5 g output r oh on resistance v h to outx inx = v s +, i outx = -100ma 3.5 r ol on resistance v l to outx inx = 0v, i outx = +100ma 3 i leak+ positive output leakage current inx = v s +, oe = 0v, outx = v s +15na i leak- negative output leakage current inx = v s +, oe = 0v, outx = v s --15na power supply i s+ v s + supply current inx = 0v and v s +0.8ma i s- v s - supply current inx = 0v and v s +-0.8ma i h v h supply current inx = 0v and v s +0.1a i l v l supply current inx = 0v and v s +0.1a switching characteristics t r rise time inx = 0v to 5v step, c l = 1nf 11 ns t f fall time inx = 5v to 0v step, c l = 1nf 12 ns t rf t r , t f mismatch c l = 1nf 1 ns t d + turn-on delay time inx = 0v to 5v step, c l = 1nf 11.5 ns t d - turn-off delay time inx = 5v to 0v step, c l = 1nf 13 ns t dd t d +, t d - mismatch c l = 1nf 1.5 ns t enable enable delay time inx = v s +, oe = 0v to 5v step, r l = 1k 12 ns t disable disable delay time inx = v s +, oe = 5v to 0v step, r l = 1k 27 ns isl7457srh
5 fn6874.1 may 16, 2011 typical performance curves (pre-rad) figure 1. switch threshold vs supply voltage figure 2. quiescent supply current vs supply voltage figure 3. ?on?-resistance vs supply voltage f igure 4. rise/fall time vs supply voltage figure 5. rise/fall time vs temperature figure 6. propagation delay time vs supply voltage low limit = 0.8v hysteresis 1.8 1.6 1.4 1.2 1.0 5.0 7.0 10 12 15 supply voltage (v) input voltage (v) t a = +25c high limit = 2.4v all inputs = 0v 2.0 1.6 1.2 0.8 0 5 7 10 12 15 supply voltage (v) supply current (ma) 0.4 t a = +25c all inputs = v s + i out = 100ma t a = +25c v l to out 9 8 6 4 2 5 7 10 12 15 supply voltage (v) ?on? resistance ( ) 3 7 5 v h to out c l = 1nf t a = +25c 25 20 15 10 5 5 7 10 12 15 supply voltage (v) rise/fall time (ns) t f t r c l = 1nf v s + = 15v 16 14 12 8 6. -50 0 50 100 125 temperature (c) rise/fall time (ns) t f t r 10 25 75 -25 25 20 15 5.0 51015 supply voltage (v) propagation delay time (ns) 10 12 7 t d- t d+ c l = 1nf t a = +25c isl7457srh
6 fn6874.1 may 16, 2011 figure 7. propagation delay time vs temperature figure 8. rise/fall time vs load capacitance figure 9. supply current per channel vs load capacitance figure 10. operating frequency vs load capacitance derating curves typical performance curves (pre-rad) (continued) c l = 1nf v s + = 15v 18 14 12 8 6 -50 0 50 100 125 temperature (c) propagation delay time (ns) 10 25 75 -25 16 t d- t d+ 140 120 100 20 0 100 1k 4.7k 10k load capacitance (pf) rise/fall time (ns) t f t r 60 2.2k 470 80 40 v s + = 15v t a = +25c v s + = v h = 10v v s - = v l = 0v f = 100khz 12 8 6 2 0 100 1k 10k load capacitance (pf) supply current (ma) 4 10 t a = +25c v s + = 15v 0 400 800 1000 load capacitance (pf) 600 200 50 40 30 20 0 operating frequency (mhz) 10 . . . . . . . . . t j = +150c t j = +125c isl7457srh
7 fn6874.1 may 16, 2011 timing diagram standard test configuration table 1. operating voltage range pin min max v s + to v s - 4.5v 16.5v v s - to gnd 0v 0v v h v s - + 2.5v v s + v l v s -v s + v h to v l 0v 16.5v v l to v s -0v 8v 90% 10% output 2.5v 5v input 0 t d + t r t d - t f 1 2 3 4 16 15 14 13 5 6 7 12 11 10 8 9 4.7f 0.1f ina inb v l inc ind 10k v s + oe outd outc v h outb outa v s + 1nf 1nf 0.1f 4.7f 1nf 1nf 0.1f 4.7f isl7457srh
8 fn6874.1 may 16, 2011 block diagram pin descriptions 16 ld flatpack name function equivalent circuit 1 ina input channel a circuit 1 2 oe output enable (reference circuit 1) 3 inb input channel b ( reference circuit 1) 4v l low voltage input pin 5 gnd input logic ground 6, 13 nc no connection 7 inc input channel c ( reference circuit 1) 8 ind input channel d ( reference circuit 1) 9v s - negative supply voltage 10 outd output channel d circuit 2 11 outc output channel c (reference circuit 2) 12 v h high voltage input pin 14 outb output channel b (reference circuit 2) 15 outa output channel a (reference circuit 2) 16 v s + positive supply voltage v s - v s - v s + v s + inx v s - v s + outx v s - v l v h 3-state control level shifter outx v l v h oe inx v s + gnd v s - isl7457srh
9 fn6874.1 may 16, 2011 application information product description the isl7457srh is a high performance, high speed quad cmos driver. each channel of the isl7457srh consists of a single p-channel high side driver and a single n-channel low side driver. these 3.5 devices will pull the output (outx) to either the high or low voltage, on v h and v l respectively, depending on the input logic signal (inx). it should be noted that there is only one set of high and low voltage pins. a common output enable (oe) pin is available on the isl7457srh. when this pin is pulled low, it will put all outputs in a high impedance state. supply voltage range and input compatibility the isl7457srh is designed to operate on nominal 5v to 15v supplies with 10% tolerance. table 1 on page 7 shows the specifications for the relationship between the v s +, v s -, v h , v l , and gnd pins. the isl7457srh does not contain a true analog switch and therefore v l should always be less than v h . all input pins are compatible with both 3.3v and 5v cmos signals. pcb layout guidelines 1. a ground plane must be used, preferably located on layer #2 of the pcb. 2. connect the gnd and v s - pins directly to the ground plane. 2. the v s +, v h and v l pins should be bypassed directly to the ground plane usin g a low-esr, 4.7f solid tantalum capacitor in parallel with a 0.1f ceramic capacitor. locate all bypass capacitors as close as possible to the respective pins of the ic. 3. keep all input and output connections to the ic as short as possible. 4. for high frequency operation above 1mhz, consider use of controlled impedance traces terminated into 50 on all inputs and outputs. power dissipation calculation when switching at high speed s, or driving heavy loads, the isl7457srh drive capability is limited by the rise in die temperature brought about by internal power dissipation. for reliable operation die temperature must be kept below t jmax (+150c). power dissipation may be calculated as shown in equation 1: where: p d is the power dissipated in the device. v s is the total power supply to the isl7457srh (from v s + to v s -). i s is the quiescent supply current. c int is the internal load capacitance (80pf max). f is the operating frequency. c l is the load capacitance. v out is the swing on the output (v h - v l ). junction temperature calculation once the power dissipation for the application is determined, the maximum junction temperature can be calculated as shown in equation 2: where: t jmax is the maximum operating junction temperature (+150c). t smax is the maximum operating sink temperature of the pcb. jc is the thermal resistance, junction-to-case, of the package . cs is the thermal resistance, case-to-sink, of the pcb. p d is the power dissipation calculated in equation 1. pcb thermal management to minimize the case-to-sink thermal resistance, it is recommended that multiple vias be placed on the top layer of the pcb directly underneath the ic. the vias should be connected to the ground plane, which functions as a heatsink. a gap filler material (i.e. a sil-pad or thermally conductive epoxy) may be used to insure good thermal contac t between the bottom of the ic and the vias. p d v s i s () c int v s 2 f () c l v out 2 f () + 1 4 + = (eq. 1) t jmax t smax ( jc cs ) p d ++ = (eq. 2) isl7457srh
10 fn6874.1 may 16, 2011 die characteristics die dimensions: 2390 m x 2445 m (94.1 mils x 96.3 mils) thickness:13.0 mils 0.5 mil interface materials glassivation type: psg and silicon nitride thickness: 0.5 m 0.05 m to 0.7 m 0.05 m top metallization type: alcusi (1%/0.5%) thickness: 1.0 m 0.1 m substrate: type: silicon isolation: junction backside finish: silicon assembly related information substrate potential: v s - additional information worst case current density: < 2 x 10 5 a/cm 2 (see figure 10) transistor count: 1142 metallization mask layout isl7457srh ina oe inb v l gnd inc v s - outd outc v h outb outa ind v s + delay isl7457srh
11 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6874.1 may 16, 2011 for additional products, see www.intersil.com/product_tree layout characteristics step and repeat: 2390 m x 2445 m the delay pad is not bonded. table 1. layout x-y coordinates pad name x ( m) y ( m) dx ( m) dy ( m) probes per pad ind 675 190 140 140 1 v s - 995 190 140 140 1 outd 2118 490 122 133 1 outc 2118 795 122 133 1 v h 2118 1039 122 345 2 2118 1211 outb 2118 1554 122 133 1 outa 2118 1861 122 133 1 v s + 1015 2140 140 140 1 ina 608 2140 140 140 1 oe 213 1993 140 140 1 inb 213 1673 140 140 1 v l 213 1331 140 345 2 213 1159 gnd 213 864 140 140 1 delay 213 585 140 140 0 inc 213 213 140 140 1 isl7457srh
12 fn6874.1 may 16, 2011 isl7457srh ceramic metal seal fl atpack packages (flatpack) notes: 1. index area: a notch or a pin one identification mark shall be located adjacent to pin on e and shall be located with- in the shaded area shown. the manufacturer?s identifi- cation shall not be used as a pin one identification mark. alternately, a tab (dimension k) may be used to identify pin one. 2. if a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. this dimension allows for off-center lid, meniscus, and glass overrun. 4. dimensions b1 and c1 apply to lead base metal only. di- mension m applies to lead pl ating and finish thickness. the maximum limits of lead dimensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is ap- plied. 5. n is the maximum number of terminal positions. 6. measure dimension s1 at all four corners. 7. for bottom-brazed lead pack ages, no organic or poly- meric materials shall be molded to the bottom of the package to cover the leads. 8. dimension q shall be measured at the point of exit (be- yond the meniscus) of the lead from the body. dimen- sion q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch -d- -c- 0.004 h a - b m d s s -a- -b- 0.036 h a - b m d s s e e a q l d a e1 seating and l e2 e3 e3 base plane -h- b c s1 m c1 b1 (c) (b) section a-a base lead finish metal pin no. 1 id area a m k16.a mil-std-1835 cdfp4-f16 (f-5a, configuration b) 16 lead ceramic metal seal flatpack package sym- bol inches millimeters note s min max min max a 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - d- 0.440 - 11.18 3 e 0.245 0.285 6.22 7.24 - e1 - 0.315 - 8.00 3 e2 0.130 - 3.30 -- e3 0.030 - 0.76 -7 e 0.050 bsc 1.27 bsc - k 0.008 0.015 0.20 0.38 2 l 0.250 0.370 6.35 9.40 - q 0.026 0.045 0.66 1.14 8 s1 0.005 - 0.13 -6 m- 0.0015 - 0.04 - n16 16- rev. 1 2-20-95

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